1. Field of the Invention
This invention relates to a highly reliable semiconductor device having a vertical bipolar transistor and LDD (Lightly Doped Drain) type MOS transistor installed on the same substrate and to a method for manufacturing the device at a low cost.
2. Description of the Prior Art
As a design rule for a semiconductor device is reduced and the number of transistors integrated in one chip is increased, it is required that a chip area is further increased. With such a tendency, it becomes necessary to arrange wirings, to which many loads are connected on the chip or to arrange a long wiring with a large capacitance. In order to drive such high capacitance loads as above at a high speed, it is preferable to apply a bi-polar transistor having a superior current driving capability as compared with that of MOS transistor and having a high trans-conductance. In turn, in view of its high integration and a low power consumption, it is preferential to apply a CMOS transistor circuit. Thus, in the recent semiconductor devices such as VLSI and ULSI, a large number of bi-CMOS transistor circuits (hereinafter referred to as "BiCMOS") capable of combining a bi-polar transistor with the CMOS transistor circuit to get merits from both transistors have been employed. These devices having much performances are utilized in TV equipment, video equipment, portable telephone equipment or a hard disk device or a high-speed memory element.
As for the semiconductor device such as a BiCMOS having a complex structure, it becomes more important to get a high performance and to reduce its number of manufacturing steps and its manufacturing cost in view of promoting its practical application or distribution.
In this case, the manufacturing steps for the general BiCMOS of the prior art will be described. The bi-polar transistor contained in BiCMOS explained here is a vertical bipolar transistor in which either npn-junction or pnp-junction corresponding to emitter/base/collector is formed in a depth direction (a vertical direction) of the substrate. Typically, the bi-polar transistor has been manufactured by a process in which a base terminal is formed in a first semiconductor film and an emitter terminal is formed by a second semiconductor film. Since either a poly-silicon film or polycide film containing impurities is normally used as these first and second semiconductor films, a constitution of such a bi-polar transistor is sometimes called "a double polysilicon constitution". The aforesaid emitter terminal is contacted with the substrate in a self-aligned manner within a window (emitter window) opened at the aforesaid base terminal, so that both terminals are insulated from each other by an insulating film covering the base terminal and an emitter side wall formed at the side wall surface of the aforesaid emitter window.
A typical manufacturing process is illustrated in FIGS. 1 to 5, in which PMOS transistor is eliminated for a sake of clarity and only NPN bi-polar transistor (NPN-Tr) and NMOS transistor are illustrated. Accordingly, description about the forming process of PMOS transistor is omitted here.
At first, an n.sup.+ type embedded collector region 2 (n.sup.+ -BL) is formed at a surface insulator of a p-type silicon substrate 1 (p-Sub). Subsequently an n-type epitaxial insulator 3 (n-Epi) is grown at its entire surface. Then, an element separating field oxide film 4 is formed in accordance with a well-known LOCOS process. An ion-implantation is carried out through this field oxide film 4 and a resist mask (not shown), whereby a p-type well 5 (p-Well) is formed. Further a p type channel stop region 6 is formed within the substrate below the field oxide film 4 by a high energy ion-implantation process. After this operation, annealing is carried out to connect the p-type well 5 and the channel stop region 6 to the silicon substrate 1.
Then, a gate oxide film 7 is formed in an active region of the silicon substrate by a thermal oxidizing process, subsequently the gate oxide film 7 is selectively removed from the base forming region of NPN-Tr so as to form a base window 7BW. Then, the first polysilicon film is deposited on an entire surface of the substrate, and, boron (BF.sub.2.sup.+) is introduced into a region acting as a base electrode and phosphorusus (P.sup.+) is embedded into a region acting as a gate electrode of NMOS by an ion-implantation process using a photo-resist (not shown). Further, the first insulator polysilicon film is processed with a patterning, the base electrode 8B is formed at the NPN-Tr part and the gate electrode 8G is formed at the NMOS part concurrently. In addition, phosphorusus (P.sup.+) with low ion concentration is introduced into the active region of the NMOS part by using an ion-implantation method so as to form an n.sup.- type LDD region. This LDD region may constitute a part adjacent to the channel end of a source/drain region 168D at the later stage, which serves for reducing a high electrical field near the drain end to improve a hot-carrier resisting property of the MOS transistor.
Then, an insulating film is deposited on the entire surface of the substrate, and the film is entirely etched-back to form a gate side wall 100G on the side wall surface of the aforesaid gate electrode 8G. At this time, a side wall 100 is also formed on the side wall surface of the base electrode 8B. In addition, under this condition, arsenic (As.sup.+) with low ion concentration is introduced into the active region so as to form a source/drain region 168D of the LDD type NMOS and the collector region 16C of NPN-Tr. FIG. 1 indicates the semiconductor devices subjected to the processes described above.
Then, a SiOx interlevel insulator film layer 101 is deposited on an entire surface of the substrate, and this SiOx interlevel insulator film layer 101 and a base electrode 8B are totally processed with patterning in an emitter-forming region at the NPN-TF part so as to open the emitter window 8EW. Boron (BF.sub.2.sup.+) is introduced through this emitter window 8EW by ion-implantation method so as to form a p-type intrinsic base region 11. FIG. 2 is illustrates the semiconductor devices subjected to the processes described above.
Then, after the insulating film is deposited on an entire surface of the substrate, a heat treatment is carried out so as to activate the impurities already fed into the active region and concurrently boron is dispersed from the base leading electrode 8B into the activated region so as to form a p.sup.- type graft base region 13. Subsequently, the aforesaid insulating film is etch backed at its entire surface so as to form an emitter side wall 12 on the inner surface of the emitter window 8EW. This emitter side wall 12 may act to insulate the base leading electrode 8B against the emitter leading electrode 14E to be described later. Subsequently, a second surface poly-silicon film is deposited on an entire surface of the substrate, arsenic (As.sup.+) becoming emitter impurities is fed in its ion form to this film, thereafter this arsenic is dispersed into the real base region 11 by heat treatment so as to form an emitter region 17. After this operation, the second insulator polysilicon film is etched in anisotropy state through a resist mask (not shown) and an emitter leading electrode 14E is formed. In FIG. 2 illustrates a completed state of processing performed up to now.
Then, as shown in FIG. 4, an SiOx interlevel insulator film layer 102 is deposited on an entire surface of the substrate. In addition, as shown in FIG. 5, this SiOx interlevel insulator film layer 102 is dry etched in the region adjacent to the emitter leading electrode 14E, and both SiOx interlevel insulator film layer 102 and 101 are dry etched in the region adjacent to each of the base leading electrode 8B, the collector leading region 16C. and the source/drain region 16SD through a resist mask not shown so as to open a connection hole 103. In addition, a well-known wiring material film is formed on the entire surface of the substrate, the film is processed in patterning to form a base electrode 104B, an emitter electrode 104E and a collector electrode 104C at the NPN-Tr part and to form source/drain electrodes 104SD at the NMOS part, respectively.